今天得到软件x-hdl，整个软件不大，好象是2.7m,有兴趣的可以来这里下载：
ftp://218.64.19.133
文件1(intall)：xhdl3.1.42.exe
文件2(crack) ：x-hdl.v3.1.30.zip（我现在只有x-hdl.v3.1.30的，没法，先用它吧）。
据介绍，用它可以把你的vhdl设计文件转换为
verilog，也可以把verilog===》vhdl。我安装后马上试了一下，
以下是我第一次试用的verilog，一个十进制计数器：
module count10(out,clk);
output out;
input clk;
reg out;
reg [2:0] count;

always @(posedge clk )
begin
count = count + 1;
if( count == 5 )
begin
count = 0;
out =!out;
end
end
endmodule

下面是用它转换vhdl的结果：---------------------------------------------------------------------------------------------
--
-- vhdl file generated by x-hdl - revision 3.1.42
-- wed oct 31 15:00:13 2001
--
-- input file : c:/my documents/xxxxxx/count5.v
-- design name : count5
-- author : 112
-- company : 112
--
-- description :
--
--
----------------------------------------------------------------------------------------------
--

entity count5 is
port (
out_xhdl1 : out std_logic;
clk : in std_logic);
end count5;

architecture translated of count5 is


signal count : std_logic_vector(2 downto 0);
signal out_xhdl1_xhdl2 : std_logic;

begin
out_xhdl1 <= out_xhdl1_xhdl2;

process
begin
wait until (clk'event and clk = '1');
count <= count + "001";
if (count = "101") then
count <= "000";
out_xhdl1_xhdl2 <= not out_xhdl1_xhdl2;
end if;
end process;

end translated;