library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counters is
port(
reset : in std_logic;
cs : in std_logic;
clk : in std_logic;
q : out std_logic_vector(11 downto 0)
);
end counters;

architecture bev of counters is
signal one,ten,hun : std_logic_vector(3 downto 0);

begin
a: process(clk, reset, cs)
begin
if(reset = '1')then
one<="0000";
elsif cs = '1' then
if clk'event and clk = '1' then
if(one="1001")then
one<="0000";
else
one<=one+1;
end if;
end if;
end if;
end process;

b: process(clk, reset, cs, one)
begin
if(reset = '1')then
ten<="0000";
elsif cs = '1' then
if clk'event and clk = '1' then
if(ten="1001" and one="1001")then
ten<="0000";
elsif(one="1001")then
ten<=ten+1;
end if;
end if;
end if;
end process;

c: process(clk, reset, cs, one, ten)
begin
if(reset = '1')then
hun<="0000";
elsif cs = '1' then
if clk'event and clk = '1' then
if(hun="1001" and ten="1001" and one="1001")then
hun<="0000";
elsif(ten="1001" and one="1001")then
hun<=hun+1;
end if;
end if;
end if;
end process ;
q<=hun&ten&one;
end bev;




--********************************************************************
--* this automatically generated test bench template has been created*
--* by active-hdl <tbgen v1.11>. copyright (c) aldec inc. *
--* *
--* this file was generated on: 10:56, 01-12-18 *
--* tested entity name: counters *
--* file name contains tested entity: $dsn\src\counter10.vhd *
--********************************************************************

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

-- add your library and packages declaration here ...

entity counters_tb is
end counters_tb;

architecture tb_architecture of counters_tb is
-- component declaration of the tested unit
component counters
port(
reset : in std_logic;
cs : in std_logic;
clk : in std_logic;
q : out std_logic_vector(11 downto 0) );
end component;

-- stimulus signals - signals mapped to the input and inout ports of tested entity
signal reset : std_logic;
signal cs : std_logic;
signal clk : std_logic;
-- observed signals - signals mapped to the output ports of tested entity
signal q : std_logic_vector(11 downto 0);

-- add your code here ...
constant clk_cycle : time := 10 ns;
begin

-- unit under test port map
uut : counters
port map
(reset => reset,
cs => cs,
clk => clk,
q => q );

-- add your stimulus here ...
rstp : process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
cs <= '1';
wait;
end process;

clkp : process
begin
clk <= '1';
wait for clk_cycle;
clk <= '0';