the cadence® allegro® system interconnect design platform enables collaborative design of high-performance interconnect across ic, package, and pcb domains. the platform's constraint-driven flow and co-design methodology optimizes system interconnect between i/o buffers and across ics, packages, and pcbs, eliminating hardware re-spins, reducing costs and design cycles, and accelerating time to market.

ongoing technological breakthroughs and fierce market demands place immense pressure on ic package designers and engineers. with the move to nanometer-scale ics, chips contain more functionality and are driven to higher performance levels than ever before. at the same time, packaging technology is undergoing rapid change, including the move to multi-layer flip-chip packaging to accommodate 1000+ i/o pins and multiple stacked die systems in package (sip) as a realistic alternative to socs. such changes are driving the need for a co-design methodology across silicon-package-board as engineers realize that, if optimal device performance and integrity are to be realized, packaging decisions cannot be made independently of the chip and the system.

ic packaging is now a critical link in the silicon-package-board design flow. with allegro package si and allegro package designer, cadence offers a robust set of capabilities targeted specifically at current and future packaging technologies, including wirebond, perimeter array flip-chip, full array flip-chip, and stacked multi-die packages.

only allegro package designer offers a unique approach to ic packaging that breaks through the norm of isolated job tasks and presents ic packaging design as a true package-to-board co-design solution.

allegro package si 600 series

allegro package si is designed to address the needs of engineers who are responsible for package-level trade-off, characterization, analysis, and model extraction. the allegro package si enhances your ability to make critical decisions regarding physical interconnect and substrate technology to improve overall performance of the i/o buffer. it reduces the effects of crosstalk, delay, simultaneous switching noise, and other sources of signal corruption. our solution uses a convergent methodology that considers the path from the silicon to package, package to board, and back to silicon.

allegro package designer 600 series

allegro package designer is a constraint-driven layout environment for the physical design of complex, high-density ic packages. allegro package designer includes all of the features and functionality for the design of advanced single-chip and multi-chip packages and modules and thick/thin film hybrids. it supports all packaging methods, including pga, qfp, bga, micro-bga, chip scale, and both flip-chip and wirebond die attach methods.

for a detailed explanation of cadence ic packaging solutions, please visit the ic packaging product page.