Contents

1.0 Introduction

2.0 HRA Programming Sequence for Multiplexed Mode

3.0 Implementing an Algorithm for Interpreting the Measured Cadence of a Call Progress Signal

• Background Information
• Algorithm Description
• Algorithm Source Code
• Energy Detect Program Algorithm
• Algorithm Source Code


1.0 Introduction

The MT90812 Integrated Digital Switch (IDX)provides the integration of several functions required in a telecom application. The purpose of this Application Note is to provide supplementary information on the application of the HRA and Energy Detect blocks of the IDX. A programming sequence for the multiplexed mode of the HRA is provided to assist the system designer with the steps required to program the IDX. The software algorithm for the Energy Detect block provides the system designer with a sample algorithm to interpret the cadence of supervisory signals.

2.0 HRA Programming Sequence for Multiplexed Mode

The HLDC Resource Allocator (HRA) module in the MT90812 supports communications over the Dchannel and provides an interface to the MT8952 HDLC Protocol Controller. The RX section of the HRA can operate in Dedicated Receive mode or Multiplexed Receive mode (RX channel Auto-hunt). The primary function of the RX channel Auto-hunt circuit is to provide the RX circuit with the next receive channel number. This section of the Application Note provides the programming sequence for the Auto-hunt mode. For the hardware architecture refer to the diagram “Typical Application Using the HDLC Resource Allocator” in the MT90812 data sheet.

The steps provided here are intended to guide the system designer with some of the programming aspects of the Auto-hunt mode. To exercise the Autohunt mode a few assumptions are made as follows:

• The system contains 16 DNICs
• The C-channels occur before D-channels on the STi/o1 stream
• The D-channel bit rate is at 16 kb/s on the STBUS.Hence the DNICs need to operate at 160 kb/s
• The peripheral connected to DNIC 2 sends the first RTS flags
• While the HRA and the HDLC receiver are busy with the D-channel slot for DNIC peripheral connected to DNIC 14 sends RTS flags

The following steps provide the initial programming steps:

• Enable the HDLC Controller for External Timing mode and idle state

• Enable the Interrupt Flag bits of the HDLC Controller as desired

• Enable the HRA by setting the EN bit high in the HRA Control register 1

• Allow C channels to occur before D channels by setting the CD bit high in the HRA Control register 1

• To enable the D channel bit rate at 16 kb/s, set the BRSEL1-0 bits to 01 in the HRA Control register 1

• In order for the Auto-hunt circuit to monitor all 16 D channels, set LOC0-7 and LOC8-15 bits to low in HRA Lock Out Registers 1 and 2 Figure 1 summarizes the Auto-hunt algorithm. Figure 2 illustrates the sequence of events in this example.

The Auto-hunt circuit will start monitoring channels 16 to 31 (bit CD=1 in the HC1 register) of stream STi1. It is assumed that the peripheral connected to DNIC 2 sends the first RTS flags. Upon detection of the RTS flag by the auto-hunt circuit, it will send a GA flag (CTS flag = 011111110 = 7F +’0’) and enable RxCEN for 2 bits per frame during channel 17 which is allocated for the DNIC 2 D-channel. A read of HRA Status register 1 should confirm that the present receive channel is channel 17 (PRX4-1 =0001) and the receive channel is latched (RXCHNL is set high).

Once the RxCEN is enabled for 2 bits per frame during channel 17, the HDLC Controller will start receiving packets from the DNIC 2 peripheral. Thereceive section of the HD