问题：
　　是不是用fpga express能编译标准的verilog hdl语言写的程序，再生成edif文件交给max+plus处理？具体如何操作？
回答一：
　　好像max+plus也能编辑verilog hdl语言写的程序,具体做法从文本编辑窗口输入程序,编译即可.
回答二：
　　还是推荐大家用synplify做综合吧，对语法的要求不严格，软件也不大。
连altera和xilinx的人都推荐我用。

回答三：
　　synplify 在综合方面好一些,但maxplus ii 的功能更全面些,我觉得.

回答四：
　　synplify速度快，但不见得综合效果好。leonardo spectrum不错，还可以综合到asic。

回答五：
　　half and half, i don't agree the viewpoints.

回答六：
　　synplify only synthesis, mp2 including all fpga application function.their
marketing focus is not same. please advise.

回答七：
　　the web-friend advise is right if your design is not large-scale, but pls notes that altera is fpga vendor, not hdl synthesis vendor. if you think your design is very large, for example, you will design with 10k100 or acek etc, at least over 5k dff application, you should apply such as fpga express or exemplar etc tools. 

回答八：
　　the web-friend is very important, i use the synplify from 1997, it is very good, fpga express embbed their core-solution.