你可以指定状态寄存器和状态机的状态。以下是一个有四种状态的普通状态机。

// these are the symbolic names for states
// 定义状态的符号名称
parameter [1:0]
s0 = 2'h0,
s1 = 2'h1,
s2 = 2'h2,
s3 = 2'h3;

// these are the current state and next state variables
// 定义当前状态和下一状态变量
reg [1:0] state;
reg [1:0] next_state;


// state_vector state
// 状态向量的转移关系
always @ (state or y or x)
begin
next_state = state;
case (state)
s0: begin
if (x) begin
next_state = s1;
end
else begin
next_state = s2;
end
end
s1: begin
if (y) begin
next_state = s2;
end
else begin
next_state = s0;
end
end
s2: begin
if (x & y) begin
next_state = s3;
end
else begin
next_state = s0;
end
end
s3: begin
next_state = s0;
end
endcase
end


always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= s0;
end
else begin
state <= next_state;
end
end


　　同样的状态机也可以用下面的代码以“one hot”编码方式实现。
// these are the symbolic names for states
// 定义状态的符号名称
parameter [1:0]
s0 = 2'h0,
s1 = 2'h1,
s2 = 2'h2,
s3 = 2'h3;

parameter [3:0]
s0 = 4'h1,
s1 = 4'h2,
s2 = 4'h4,
s3 = 4'h8;

// these are the current state and next state variables
// 定义当前状态和下一状态变量
reg [3:0] state;
reg [3:0] next_state;


// state_vector state
// 状态向量的转移关系
always @ (state or y or x)
begin
next_state = state;
case (1)
state[s0]: begin
if (x) begin
next_state = 1 << s1;
end
else begin
next_state = 1 << s2;
end
end
state[s1]: begin
if (y) begin
next_state = 1 << s2;
end
else begin
next_state = 1 << s0;
end
end
state[s2]: begin
if (x & y) begin
next_state = 1 << s3;
end
else begin
next_state = 1 << s0;
end
end
state[s3]: begin
next_state = 1 << s0;
end
endcase
end


always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= 1 << s0;
end
else begin
state <= next_state;
end
end