Active and Passive Devices
发布时间:2008/6/5 0:00:00 访问次数:601
active devices for r.f. include gaas fets, silicon bipolars and nmos and possibly pmos transistors. standard library types for a given process vendor can usually be adapted to the requirement, and are strongly advocated to avoid layout errors.
passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in gaas circuits, but less so in silicon because the losses are greater.
some sample device layouts are shown below:
fig 2 : nmos transistor, designed to a 2 lambda rule set, for 0.8 micron process
one feature of many layout editors is the use of a 'lambda;' based rule set. the designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. then, at a given process foundry, this rule may be interpreted as required. for example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. this is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
fig 3 : pmos transistor
similarly, a pmos device is shown above. in this case, the device is surrounded by an n-well, for correct polarity of conductors and isolation.
fig 4 : vertical npn transistor
a more complex structure, not always available on mos processes, is a vertical npn bipolar transistor, as above. again, a recommended layout from the process vendor should be used in this instance if possible.
fig 5, lateral pnp
active devices for r.f. include gaas fets, silicon bipolars and nmos and possibly pmos transistors. standard library types for a given process vendor can usually be adapted to the requirement, and are strongly advocated to avoid layout errors.
passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in gaas circuits, but less so in silicon because the losses are greater.
some sample device layouts are shown below:
fig 2 : nmos transistor, designed to a 2 lambda rule set, for 0.8 micron process
one feature of many layout editors is the use of a 'lambda;' based rule set. the designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. then, at a given process foundry, this rule may be interpreted as required. for example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. this is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
fig 3 : pmos transistor
similarly, a pmos device is shown above. in this case, the device is surrounded by an n-well, for correct polarity of conductors and isolation.
fig 4 : vertical npn transistor
a more complex structure, not always available on mos processes, is a vertical npn bipolar transistor, as above. again, a recommended layout from the process vendor should be used in this instance if possible.
fig 5, lateral pnp
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passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in gaas circuits, but less so in silicon because the losses are greater.
some sample device layouts are shown below:
fig 2 : nmos transistor, designed to a 2 lambda rule set, for 0.8 micron process
one feature of many layout editors is the use of a 'lambda;' based rule set. the designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. then, at a given process foundry, this rule may be interpreted as required. for example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. this is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
fig 3 : pmos transistor
similarly, a pmos device is shown above. in this case, the device is surrounded by an n-well, for correct polarity of conductors and isolation.
fig 4 : vertical npn transistor
a more complex structure, not always available on mos processes, is a vertical npn bipolar transistor, as above. again, a recommended layout from the process vendor should be used in this instance if possible.
fig 5, lateral pnp
passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in gaas circuits, but less so in silicon because the losses are greater.
some sample device layouts are shown below:
fig 2 : nmos transistor, designed to a 2 lambda rule set, for 0.8 micron process
one feature of many layout editors is the use of a 'lambda;' based rule set. the designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. then, at a given process foundry, this rule may be interpreted as required. for example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. this is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
fig 3 : pmos transistor
similarly, a pmos device is shown above. in this case, the device is surrounded by an n-well, for correct polarity of conductors and isolation.
fig 4 : vertical npn transistor
a more complex structure, not always available on mos processes, is a vertical npn bipolar transistor, as above. again, a recommended layout from the process vendor should be used in this instance if possible.
fig 5, lateral pnp
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