要看数据长度了，如果数据量不大，可以直接用寄存器：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity buff_reg is
--generic(strb_del,en_del,o_del: time);
port (strb,ds1,ds2: in std_logic;
di :in std_logic_vector(7 downto 0);
do: out std_logic_vector(7 downto 0));
end buff_reg ;

architecture alg of buff_reg is
signal enable:std_logic;
signal reg : std_logic_vector(1 to 8);
begin
p1: process(strb)
begin
wait until strb='1';
reg<= di ;--after strb_del;
end process p1;

p2: process(ds1,ds2)
begin
enable<= ds1 and not ds2 ;--after en_del;
end process p2;

p3: process(reg ,enable)
begin
if enable='1' then
do<= reg ;--after o_del;
else
do<= "00000000" ;--after o_del;
end if;
end process p3;
end alg;
其实就是一个缓存